Integrated circuits use conductive interconnects to wire together the individual devices on a semiconductor substrate, or to communicate externally to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. As device geometry continued to scale down to 65-nm-node technology and sub-65-nm technology, the requirement of continuous barrier/seed layer with good step coverage along high aspect ratio geometry to provide void free copper filling becomes challenging. The motivation to go to ultra thin and conformal barrier in 65-nm-node or sub-65-nm-technology is to reduce the barrier's impact on via and line resistance. However, poor adhesion of copper to the barrier layer could cause delamination between the barrier layer and copper during processing or thermal stressing that poses a concern on electro-migration and stress-induced voiding.
In view of the foregoing, there is a need for systems and processes that enable deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect.